hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 1 - hanbit electronics co.,ltd. rev.1.0 (august.2002) general description the hmd 4m36m 9g is a 4m x 36 bit dynamic ram high - density memory module. the module hmd 4m36m 9g consists of eight cmos 4m x 4 bit drams in 24 - pin soj packages and one cmos 4m x 4 bit quad /cas dram in 28 - pin soj package mounted on a 72 - pin, double - sided, fr - 4 - printed circuit board. a 0.1uf or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components may be powered from a single 5v dc power supply and all inputs and outputs are ttl - compatible. features w part identification hmd4m36m9g - 2,048 cycles/32ms ref. gold lead hmd4m36m9ag - 4,096 cycles/64ms ref. gold lead w access times : 50ns, 60ns w high - density 16mbyte design w 2 , 048 cycles/32ms ref. w single + 5v 0.5v power supply w jedec standard pinout w fast page mode o peration w /cas - before - /ras refresh capability w ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 50 n s access - 5 60 n s access - 6 w packages 72 - pin simm m performance range s peed trac tcac trc 5 50ns 13ns 90ns 6 60ns 15ns 110ns presence detect pins pin 50ns 60ns pd1 vss vss pd2 nc nc pd3 vss nc pd4 vss nc pin symbol pin symbol pin symbol 1 vss 25 dq2 4 49 dq 9 2 dq0 26 dq7 50 dq2 7 3 dq1 8 27 dq2 5 51 dq 10 4 dq1 28 a7 52 dq2 8 5 dq1 9 29 a11 53 dq1 1 6 dq2 30 vcc 54 dq2 9 7 dq 20 31 a8 55 dq1 2 8 dq3 32 a9 56 dq 30 9 dq 21 33 nc 57 dq1 3 10 vcc 34 /ras2 58 dq 31 11 nc 35 dq26 59 vcc 12 a0 36 dq8 60 dq 32 13 a1 37 dq1 7 61 dq1 4 14 a2 38 dq35 62 dq 33 15 a3 39 vss 63 dq1 5 16 a4 40 /cas0 64 dq3 4 17 a5 41 /cas2 65 dq1 6 18 a6 42 /cas3 66 nc 19 a10 43 /cas1 67 vss 20 dq4 44 /ras0 68 pd2 21 dq2 2 45 nc 69 pd3 22 dq5 46 nc 70 pd4 23 dq2 3 47 /w e 71 nc 24 dq6 48 nc 72 v ss 16mbyte(4mx36) fast page with parity mode, 2k/4k refresh part no. hm d4m36m9g, hmd4m36m9ag a0 C a11 : address input(4k ref.) a0 C a10 : address input(2k ref.) *a11 is used for only hmd4m36m9ag pin assignment
hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 2 - hanbit electronics co.,ltd. rev.1.0 (august.2002) functional block dia gram dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 1 dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 2 dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 4 dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 5 dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 6 dq0 cas dq1 ras d q2 oe w a0 - a10(a11) dq3 u 7 dq0 cas dq1 ras dq2 oe w a0 - a10(a11) dq3 u 8 d q0 cas dq1 ras dq2 oe w a0 - a10 (a11)dq3 u 9 cas0 cas0 dq0 cas0 dq1 cas0 dq2 ras dq3 oe w a0 - a10(a11) u 3 /cas0 /ras0 /cas1 /cas2 /cas3 /w e a0 - a10(a11) dq0 - dq3 dq4 - dq7 dq9 - dq12 dq13 - dq16 dq8 dq17 dq26 dq35 dq18 - dq21 dq22 - dq25 dq27 - dq30 dq31 - d q34 vcc vss 0.1uf or 0.22uf capacitor for each dram /ras2
hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 3 - hanbit electronics co.,ltd. rev.1.0 (august.2002) absolute maximum rat ings parameter symbol ratin g voltage on any pin relative to vss v in ,out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 9w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect devi ce reliability. recommended dc opera ting conditions (voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics symbol speed min max units i cc1 - 5 - 6 - - 990 900 ma ma i cc2 - 18 ma i cc3 - 5 - 6 - - 990 900 ma ma i cc4 - 5 - 6 - - 810 720 ma ma i cc5 - 9 ma i cc6 - 5 - 6 - - 990 900 ma ma i l(l) i o(l) - 40 - 40 45 5 m a m a v oh v ol 2.4 - - 0.4 v v i cc1 : operating current * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min )
hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 4 - hanbit electronics co.,ltd. rev.1.0 (august.2002) i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : ou tput leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a10) c in1 - 70 pf input capacitance (/w e ) c in2 - 80 pf input capacitance (/ras0, /ras2) c in3 - 80 pf input capacitance (/cas0 - /cas3) c in4 - 40 pf input / output capacitance (dq0 - 35 ) c dq - 17 p f ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle time t rc 90 110 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 0 0 ns output buffer turn - off delay t off 0 13 0 15 ns transition time (rise and fall) t t 3 50 3 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 50 60 ns /cas pulse width t cas 13 10k 15 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns r ow address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns
hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 5 - hanbit electronics co.,ltd. rev.1.0 (august.2002) column address hold time t cah 10 10 ns column address hold referenced to /ras t ar 40 45 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command hold referenced to /ras t wcr 40 45 ns writ e command pulse width t wp 10 10 ns write command to /ras lead time t rwl 15 15 ns write command to /cas lead time t cwl 13 15 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 10 15 ns data - in hold referenced to /ras t dhr 40 45 ns ref resh period 2k ref. t ref 32 32 ns write command set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 5 5 ns /cas hold time (c - b - r refresh) t chr 10 10 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cp a 30 35 ns fast page mode cycle time t pc 35 40 ns /cas precharge time (fast page) t cp 10 10 ns /ras pulse width (fast page) t rasp 50 200k 60 200k ns /w e to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w e to /ras hold time (c - b - r refresh) t wrh 10 10 ns /cas precharge(c - b - r counter test) t cpt 20 20 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (m ax) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 2ttl loads and 100pf . 4. operation within the t rcd(max) li mit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are refere nced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referen ced to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the s pecified t rad(max) limit. then access time is controlled by t aa .
hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 6 - hanbit electronics co.,ltd. rev.1.0 (august.2002) timing diagram please refer to attached timing diagram chart (i) packaging informatio n simm design o r dering information part number density org. package refresh c ycle vcc speed hmd4m36m9g - 5 16mbyte 4mx 36bit 72 pin - simm 2,048 cycles 32ms ref. 5.0v 50ns hmd4m36m9ag - 5 16mbyte 4mx 36bit 72 pin - simm 4,096 cycle 64ms ref. 5.0v 50ns hmd4m36m9g - 6 16mbyte 4mx 36bit 72 pin - simm 2,048 cycles 32ms ref. 5.0v 60ns hmd4m36m9 ag - 6 16mbyte 4mx 36bit 72 pin - simm 4,096 cycle 64ms ref. 5.0v 60ns 1.2 7 0.08 mm 0.25 mm max 2.54 mm min 1.27 mm gold : 1.04 0. 10 mm solder:0.914 0.10mm
hanbi t hm d4m36m9g, hmd4m36m9ag url:www.hbe.co.kr - 7 - hanbit electronics co.,ltd. rev.1.0 (august.2002)
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